1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of portions that operate based on a plurality of clocks of different frequencies, and a method of designing the semiconductor device. More particularly, this invention is concerned with a semiconductor device having an internal block that operates at a high speed and a block that operates at a low speed and interfaces with outside circuits, and a method of designing the semiconductor device.
2. Description of the Related Art
In recent years, semiconductor devices have been designed to operate at higher speeds. This trend is even more obvious in CPUs. The operating speeds of internal components of the CPU may be raised but it is hard for external devices, including semiconductor devices connected to the CPU and various input and output units, to operate at the same speed as the CPU. For this reason, an interface block is often included as a peripheral LSI to be incorporated in or connected to the CPU. The interface block links a portion that operates based on a first high-frequency clock and a portion that operates based on the second low-frequency clock. In the interface block, therefore, portions that operate synchronously with two clocks of different frequencies coexist.
As far as a circuit having two portions that operate based on clocks of different frequencies is concerned, it is designed on the assumption that there are two blocks that operate synchronously with two clocks. Specifically, the circuit is designed on the assumption that there are two different clock sources and there are two portions that operate synchronously with two different clocks. When a plurality of clocks of different frequencies exist in one block, circuits that operate synchronously with different clocks coexist in the block. Moreover, internal control signals make a transition according to complex timing. This poses a problem that it becomes more difficult to inspect the timing than when the circuit is designed on the condition that only one clock is used. Besides, when a block has portions that operate synchronously with a plurality of clocks, every time such a block is designed, the plurality of portions must be prepared in one-to-one correspondence with the clocks.
Assume that a block is designed to include a plurality of state machines which operate based on a plurality of clocks. In this case, the descriptions of the operations of the block and the capabilities thereof including an RTL (register transfer level) to be written with a hardware description language HDL become complex. Besides, the number of uncertain elements increases. This poses a problem that the possibility of an occurrence of a drawback becomes more likely.